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551 sed1722/24 n description the sed1722/24 is an 80 dot matrix lcd segment (column) driver for driving high-capacity lcd panels at duty cycles higher than 1/100 (up to 1/500). the lsi features a wide range of lcd drive voltages. the device uses a high-speed daisy-chain enable system which decreases power consumption and eliminates the need for separate enable signals for each driver. the sed1722/24 is used in conjunction with the sed1733f (100-bit output common driver) to drive a large- capacity dot matrix lcd panel. ? supports display blanking ? low output resistance ? ability to adjust offset bias of the lcd source from v dd ? low output impedance ........... 1k w ? wide range of lcd voltage .... 14 to 40v ? supply voltage ........................ 4.5 to 5.5v ? package .................. qfp-5 100 pins (f oa ) al pad (d oa ) n features ? low-power high-speed cmos technology ? 80-bit segment (column) driver ? high-speed data bus .............. 4-bit (sed1722) 8-bit (sed1724) ? duty cycle ............................... 1/100 to 1/500 ? shift clock frequency .............. 12 mhz ? adjustable lcd drive voltages ? selectable output shift direction n system block diagram sed1722 sed1722 sed1722 sed1722 lcd contr 320 seg 200 com duty: 1/200 sed1733 sed1733 80 80 80 80 100 d0 ~ d3, d0~d7 (sed1724) xscl yscl yd lp, fr 100 cmos lcd driver ? cmos 80-bit segment driver
552 sed1722/24 n block diagram ? sed1722 ? sed1724 v2, v3 v ddh gnd fr inh lp d0 ~ d3 shl eio1 eio2 xscl o0 o79 lcd driver, 80 bits level shifter, 80 bits latch, 80 bits two?ay shift register voltage control enable control data control v cc gnd 4 v2, v3 v ddh gnd fr inh lp d0 ~ d3 d4 ~ d7 shl eio1 eio2 xscl o0 o79 lcd driver, 80 bits level shifter, 80 bits latch, 80 bits two?ay shift register voltage control enable control data control v cc 4 4
553 pin name i/o function qty o0 to 79 o to output the driving segment (column). 80 the output changes at the lp fall edge. d0 to d3 i to input display data. 4 (sed1722) h: selection data, l: non-selection data d0 to d7 i to input display data. 8 (sed1724) h: selection data, l: non-selection data xscl i to input shift clock for display data (fall edge trigger) 1 lp i to input latch pulse for display data (fall edge trigger) 1 ei01 i/o enable input and output: 2 ei02 input or output is set on the shl input level. output is reset by an input to lp and falls to l automatically when 80-bit data is completely fetched in. shl i to select shift direction and to input input-output control data for 1 the eio terminal. when the data are input to (d0, d1,.. d7) terminals in the order of (a, b, .. g, h), (i,.. o, p) ... (s, t,.. y, z), relations between data and segment outputs come to be as per the following table: shl o (seg output) eio 0 1 2 3 4 ...... 77 78 79 1 2 h a b c d e ...... x y z input output l z y x w v ...... c b a output input note: the relations between data and segment outputs are set irrespectively to number of shift locks. fr i to input ac signal for lcd driving output. 1 v cc , gnd power logic power supply, gnd: 0 v, v cc : +5 v 2 supply v ddh power power supply for lcd driving circuit 1 supply v ddh : +14 v to 40 v, (liquid crystal driving selection level) v2, v3 power power supply for driving liquid crystal 2 supply v ddh 3 v2 3 7/9 v ddh , 2/9 v ddh 3 v3 3 gnd inh i forced blank input 1 output on the l level are forced to non-selection level. n pin description - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - sed1722/24
554 sed1722/24 n electrical characterisitcs ? absolute maximum ratings parameter symbol ratings unit supply voltage (1) v cc C0.3 to +7.0 v supply voltage (2) v ddh C0.3 to +45.0 v supply voltage (3) v2, v3 C0.3 to v ddh +0.3 v input voltage v i C0.3 to v cc +0.3 v output voltage v o C0.3 to v cc +0.3 v eio output current i o1 20 ma lcd circuit output current i o2 20 ma operating temperature t opr C20 to +75 c storage temperature t stg C65 to +150 c (gnd = 0 v) note 1. let the v2 and v3 voltages maintain the condition, v ddh 3 v2 3 v3 3 gnd, all the time. note 2. if the logic circuit power supply comes to float power-supply voltage supply voltage is applied to the liquid crystal driving circuit, the lsi may be broken permanently. so, prevent the logic circuit power supply from floating. pay special attention to the power supply sequence when the system is switched on or off. v cc gnd v ddh v2 v3 gnd 5v 40v
555 sed1722/24 ? dc electrical characteristics parameter symbol condition terminal min typ max unit supply voltage (1) v cc v cc 4.5 5.0 5.5 v recommended supply voltage v ddh v ddh 14.0 40.0 v operable voltage v ddh function v ddh 8.0 v supply voltage (2) v2 recommendation value v2 7/9v ddh v ddh v supply voltage (3) v3 recommendation value v3 gnd 2/9v ddh v high level input voltage v ih 0.8v cc v cc v low level input voltage v il gnd 0.2v cc v high level output voltage v oh i oh = C0.6 ma eio1, eio2 v cc C0.4 v cc v low level output voltage v ol i ol = 0.6 ma gnd 0.4 v input leak current i li gnd 3 v in 3 v cc 2.0 m a input-output leak current i li/o gnd 3 v in 3 v cc eio1, eio2 5.0 m a static current i gnd v ddh = 14.0 to 40.0 v gnd 25 m a v ih = v cc , v il = gnd output resistance. r seg d v on v ddh =+30.0v *1 0.7 1.8 = 0.5v v ddh =+20.0v o0 to 0.8 2.2 k w v ddh =+14.0v o79 1.0 2.6 current consumed (1) i cc v cc 0.5 1.5 ma current consumed (2) i ddh v ddh 0.2 1.5 ma input terminal capacity c i 8 pf freq.=1 mhz, t a = 25 c i/o terminal capacity c i/o eio1, eio2 15pf (unless otherwise specified, gnd=0v, v cc = +5.0v 10%, t a = C20 to 75 c) eio1, eio2, d0 to d3: (sed1722) d0 to d7 (sed1724), xscl, shl, fr, lp, inh d0 to d3: (sed1722) d0 to d7 (sed1724), shl, xscl, lp, fr, inh v cc = +5.0 v, v ih = v cc, v il = gnd, f xscl =5.38 mhz, f lp =33.6 khz, f fr =70 hz; input data: to be inverted 1 bit/1h. no load v cc = +5.0 v, v3 = +4.0 v, v2 = +26.0 v, v ddh =+30.0v other conditions are same as those of i cc d0 to d3: (sed1722) d0 to d7 (sed1724), shl, xscl, lp, fr, inh *1. the output resistance is specified within the ranges of the supply voltages (2) and (3).
556 ? ac electrical characteristics input timing characteristics parameter symbol condition min typ max unit xscl cycle t c 83 ns xscl high level pulse width t wch 30 ns xscl low level pulse width t wcl 30 ns data setup time t ds 30 ns data hold time t dh 20 ns xscl to lp rise time t ld 0ns lp to xscl fall time t lh 200 ns lp high level pulse width t wlh see note 70 ns fr delay allowable time t df C300 300 ns eio setup time t sue 36 ns note: t wlh is the time when lp is h and xscl is l (v cc = 5.0 v 10%, t a = C20 to 75 c) t wlh t df t lh t c t wcl t wch t dh t ds t sue t ld fr lp xscl d0~d3: sed1722 d0~d7: sed1724 eio1,2 (in) ? v ih = 0.8 x v cc v il = 0.2 x v cc sed1722/24
557 sed1722/24 t lsd t dcl t frsd fr lp xscl eio1, 2 (out) inh o output t er t lsd v ih = 0.8 x v cc v il = 0.2 x v cc v oh = 0.8 x v cc v ol = 0.2 x v cc output timing characteristics parameter symbol conditions min typ max unit eio reset time t er c l = 15 pf 120 ns eio output delay time t dcl 45ns lp to output delay time t lsd 0.5 m s fr to output delay time t frsd c l = 100 pf 0.7 m s inh to output delay time t pdinh 0.5 m s (v cc = +5.0 v 10%, v ddh = 14.0 to 40.0 v, t a = C20 to 75 c)
558 sed1722/24 n timing diagram when it is 1/240 duty (example for reference) 1 240 lp lp xscl d0 to d7 eio 1 eio 2 eio n latch data fr 1234 239240 240 239 1 123 10 1 2 3 10 1 2 3 10 1 2 3 10 1 1 n to are the driver? cascade numbers. 2 lp latch data hlhl hl hlhl hl hlhl lh fr v ddh v2 v3 gnd * * in high-speed data transmission, the xscl period may need to be longer in the lp pulse insertion timing, so as to secure the lp ? xscl (t lh ) standard.
559 (combination of sed1724 with sed1733) sed1733 dio1 dio2 dio4 50 50 50 50 50 50 dio1 yscl shl fr inh d0 ~ d7 shl lp xscl liquid crystal panel (640 x 400 dots) 80 sed1724 eio1 eio2 80 sed1724 eio1 eio2 80 sed1724 eio1 eio2 80 sed1724 eio1 eio2 dio3 dio1 dio2 dio4 dio3 dio1 dio2 dio4 dio3 sed1733 sed1733 n example of reference circuit sed1733 dio1 dio2 di4 50 50 50 50 50 50 dio1 yscl shl fr inh d0 ~ d3 shl lp xscl liquid crystal panel (640 x 400 dots) 80 sed1722 eio1 eio2 80 sed1722 eio1 eio2 80 sed1722 eio1 eio2 80 sed1722 eio1 eio2 dio3 dio1 dio2 di4 dio3 dio1 dio2 di 4 dio3 sed1733 sed1733 (combination of sed1722 with sed1733) sed1722/24
560 sed1722/24 n package dimensions ? sed1722f 0a , sed1724f 0a o 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 o 30 o 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 o 0 o 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 o 79 eio2 eio1 d0 d1 d2 d3 nc/d4 nc/d5 nc/d6 nc/d7 shl xscl inh lr fr v cc v2 v3 gnd v ddh index sed1722f oa / sed1724f oa (sed1722/sed1724) nc: no connection is required 19.6 0.4 index 81 100 50 31 130 80 51 25.6 0.4 20 0.1 0.65 0.1 0.30 0.1 14 0.1 1.5 0.3 0.15 0.05 2.7 0.1 0 ~12 2.8 ? plastic qfp5-100 pin
561 pad x y pad x y pad x y number name ( m m) ( m m) number name ( m m) ( m m) number name ( m m) ( m m) 1 o 50 C2488 2432 35 d2 C1100 C2432 69 o 18 2738 610 2 o 51 C2488 2432 36 d3 C900 C2432 70 o 19 2738 785 3 o 52 C2738 2222 37 nc/d4 C700 C2432 71 o 20 2738 960 4 o 53 C2738 2022 38 nc/d5 C500 C2432 72 o 21 2738 1135 5 o 54 C2738 1835 39 nc/d6 C300 C2432 73 o 22 2738 1310 6 o 55 C2738 1660 40 nc/d7 C100 C2432 74 o 23 2738 1485 7 o 56 C2738 1485 41 shl 100 C2432 75 o 24 2738 1660 8 o 57 C2738 1310 42 xscl 300 C2432 76 o 25 2738 1835 9 o 58 C2738 1135 43 inh 500 C2432 77 o 26 2738 2022 10 o 59 C2738 960 44 lp 700 C2432 78 o 27 2738 2222 11 o 60 C2738 785 45 fr 900 C2432 79 o 28 2738 2432 12 o 61 C2738 610 46 v cc 1100 C2432 80 o 29 2488 2432 13 o 62 C2738 435 47 v2 1300 C2432 81 o 30 2000 2432 14 o 63 C2738 260 48 v3 1500 C2432 82 o 31 1750 2432 15 o 64 C2738 85 49 gnd 1750 C2432 83 o 32 1500 2432 16 o 65 C2738 C85 50 v ddh 2000 C2432 84 o 33 1300 2432 17 o 66 C2738 C260 51 o 0 2488 C2432 85 o 34 1100 2432 18 o 67 C2738 C435 52 o 1 2738 C2432 86 o 35 900 2432 19 o 68 C2738 C610 53 o 2 2738 C2222 87 o 36 700 2432 20 o 69 C2738 C785 54 o 3 2738 C2022 88 o 37 500 2432 21 o 70 C2738 C960 55 o 4 2738 C1835 89 o 38 300 2432 22 o 71 C2738 C1135 56 o 5 2738 C1660 90 o 39 100 2432 23 o 72 C2738 C1310 57 o 6 2738 C1485 91 o 40 C100 2432 24 o 73 C2738 C1485 58 o 7 2738 C1310 92 o 41 C300 2432 25 o 74 C2738 C1660 59 o 8 2738 C1135 93 o 42 C500 2432 26 o 75 C2738 C1835 60 o 9 2738 C960 94 o 43 C700 2432 27 o 76 C2738 C2022 61 o 10 2738 C785 95 o 44 C900 2432 28 o 77 C2738 C2222 62 o 11 2738 C610 96 o 45 C1100 2432 29 o 78 C2738 C2432 63 o 12 2738 C435 97 o 46 C1300 2432 30 o 79 C2488 C2432 64 o 13 2738 C260 98 o 47 C1500 2432 31 eio2 C2000 C2432 65 o 14 2738 C85 99 o 48 C1750 2432 32 eio1 C1750 C2432 66 o 15 2738 85 100 o 49 C2000 2432 33 d0 C1500 C2432 67 o 16 2738 260 34 d1 C1300 C2432 68 o 17 2738 435 n pad coordinates n pad layout (sed1722d 0a , sed1724d 0a) 100 1 (0, 0) y x chip dimensions 5.81 mm 5.20 mm pad pitch 0.160 mm (min.) chip thickness 0.400 0.025 mm aluminum pad opening 100 m m 100 m m (all terminals) sed1722/24
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